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Claim Veri - Verilog wins in EDA

Category: Science & Technology:Computer Industry JUDGED at 0
Owner:20
Judge:97, Loophole
created:1995/05/16
due date:2000/06/01

The Claim

The Verilog language, originally developed by Cadence Design Systems and as now standardized by Open Verilog International wins in the EDA marketplace.

The claim is YES if Verilog is understood to be a better design language that is more suitable for design expression, lends itself to more efficient simulators and provides better input to synthesis and test compilers relative to its competitor VHDL.

The affirmation of this judgement is defined by this recognition in any one of the (then-current) top four independent EDA vendors by virtue of their support for the Verilog language to the exclusion of the VHDL language.

Currently the top-four independent EDA vendors are

Background:
The culture here is that for many years there have been ongoing debates about whether VHDL is ``suitable'' or whether Verilog is a ``better'' language than VHDL. To wit:

  • Verilog ``C-like'' (it uses many C-type constructs) and is therefore in tune with ``designers needs.'' Verilog as implemented by Cadence's Verilog XL product is weakly typed just as C is; you get most of your errors at final-link time but not a module-compile time. There are many after-market ``lint-type'' products that fix this. Verilog is therefore a good design language.
    Until the advent of Open Verilog International, Verilog was a proprietary standard of Cadence Design Systems. Many people still think it is as you don't do Verilog until you ``do what Cadence's Verilog XL does.''
  • VHDL on the other hand is ``Ada-like'' (it was explicitly derived from Ada). VHDL is strongly-typed and you get many errors at compile time; your modules must be compiled after all modules that they use. VHDL has overloading. VHDL is a more ``complex'' language than Verilog [see Proceedings of DAC94]. VHDL is an IEEE standard (IEEE 1076-1987, reaffirmed in 1992). VHDL is also a U.S. DoD mandated standard (if you do business with the government you must provide a VHDL model of your part). VHDL is therefore a bad design language.

This claim is based on a news article by John Cooley (jcooley@world.std.com), entitled Verilog Won & VHDL Lost? -- You Be The Judge! that reports a purported ``bake off'' of the two languages using professional designers.

A copy of the article is also available separately.

Verilog
VHDL

Judge's Statement

I will judge based on the wording of the claim unless it is found to be ambiguous. Such ambiguities will be resolved based on my perception of the author's intent.

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