The Verilog language, originally developed by Cadence Design Systems and as now standardized by Open Verilog International wins in the EDA marketplace.
The claim is YES if Verilog is understood to be a better design language that is more suitable for design expression, lends itself to more efficient simulators and provides better input to synthesis and test compilers relative to its competitor VHDL.
The affirmation of this judgement is defined by this recognition in any one of the (then-current) top four independent EDA vendors by virtue of their support for the Verilog language to the exclusion of the VHDL language.
Currently the top-four independent EDA vendors are
Background: The culture here is that for many years there have been ongoing debates about whether VHDL is ``suitable'' or whether Verilog is a ``better'' language than VHDL. To wit:
This claim is based on a news article by John Cooley (firstname.lastname@example.org), entitled Verilog Won & VHDL Lost? -- You Be The Judge! that reports a purported ``bake off'' of the two languages using professional designers.
A copy of the article is also available separately.
I will judge based on the wording of the claim unless it is found to be ambiguous. Such ambiguities will be resolved based on my perception of the author's intent.